//bram
module sirv_sim_ram_itcm 
#(parameter DP = 512,
  parameter FORCE_X2ZERO = 0,
  parameter DW = 32,
  parameter MW = 4,
  parameter AW = 32 
)
(
  input             clk, 
  input  [DW-1  :0] din, 
  input  [AW-1  :0] addr,
  input             cs,
  input             we,
  input  [MW-1:0]   wem,
  output [DW-1:0]   dout
);

    wire [MW-1:0] wen;
    wire ren;
    wire [DW-1:0] dout_pre;
    
    assign ren = cs & (~we);
    assign wen = ({MW{cs & we}} & wem);

    blk_mem_gen_itcm u_itcm(
            .clka(clk),
            .addra(addr),
            .dina(din),
            .wea(wen),
            .clkb(clk),
            .addrb(addr),
            .doutb(dout_pre),
            .enb(ren)
        );
   genvar i;
   generate
  
   if(FORCE_X2ZERO == 1) begin: force_x_to_zero
      for (i = 0; i < DW; i = i+1) begin:force_x_gen 
          `ifndef SYNTHESIS//{
         assign dout[i] = (dout_pre[i] === 1'bx) ? 1'b0 : dout_pre[i];
          `else//}{
         assign dout[i] = dout_pre[i];
          `endif//}
      end
   end
   else begin:no_force_x_to_zero
     assign dout = dout_pre;
   end
  endgenerate

endmodule
//bram
module sirv_sim_ram_dtcm 
#(parameter DP = 512,
  parameter FORCE_X2ZERO = 0,
  parameter DW = 32,
  parameter MW = 4,
  parameter AW = 32 
)
(
  input             clk, 
  input  [DW-1  :0] din, 
  input  [AW-1  :0] addr,
  input             cs,
  input             we,
  input  [MW-1:0]   wem,
  output [DW-1:0]   dout
);

    reg [AW-1:0] addr_r;
    wire [MW-1:0] wen;
    wire ren;
    wire [DW-1:0] dout_pre;
    
    assign ren = cs & (~we);
    assign wen = ({MW{cs & we}} & wem);

    blk_mem_gen_dtcm u_dtcm(
        .clka(clk),
        .addra(addr),
        .dina(din),
        .wea(wen),
        .clkb(clk),
        .addrb(addr),
        .doutb(dout_pre),
        .enb(ren)
    );

    genvar i;

  generate
   if(FORCE_X2ZERO == 1) begin: force_x_to_zero
      for (i = 0; i < DW; i = i+1) begin:force_x_gen 
          `ifndef SYNTHESIS//{
         assign dout[i] = (dout_pre[i] === 1'bx) ? 1'b0 : dout_pre[i];
          `else//}{
         assign dout[i] = dout_pre[i];
          `endif//}
      end
   end
   else begin:no_force_x_to_zero
     assign dout = dout_pre;
   end
  endgenerate
endmodule



/*  dist_ram
module sirv_sim_ram_itcm
#(parameter DP = 512,
  parameter FORCE_X2ZERO = 0,
  parameter DW = 32,
  parameter MW = 4,
  parameter AW = 32 
)
(
  input             clk, 
  input  [DW-1  :0] din, 
  input  [AW-1  :0] addr,
  input             cs,
  input             we,
  input  [MW-1:0]   wem,
  output [DW-1:0]   dout
);

 //reg [DW-1:0] mem_r [0:DP-1];
 reg [AW-1:0] addr_r;
 wire [MW-1:0] wen;
 wire ren;

 wire [DW-1:0] dout_pre,spo,din_temp,wen_ext;
 //reg wen_ext;
 
 assign din_temp = (wen_ext & din) | (~wen_ext &spo);
 assign wen = ({MW{cs & we}} & wem);
 assign wen_ext={ {8{wen[7]}},{8{wen[6]}},{8{wen[5]}},{8{wen[4]}},{8{wen[3]}},{8{wen[2]}},{8{wen[1]}},{8{wen[0]}}};
    
    dist_mem_gen_rewr u_rewr(
        .a(addr),
        .d(din_temp),
        .dpra(addr_r),
        .clk(clk),
        .we(we),
        .spo(spo),
        .dpo(dout_pre)
    );

    assign ren = cs & (~we);
    always @(posedge clk)
    begin
        if (ren) begin
            addr_r <= addr;
        end
    end
    genvar i;
  

  generate
   if(FORCE_X2ZERO == 1) begin: force_x_to_zero
      for (i = 0; i < DW; i = i+1) begin:force_x_gen 
          `ifndef SYNTHESIS//{
         assign dout[i] = (dout_pre[i] === 1'bx) ? 1'b0 : dout_pre[i];
          `else//}{
         assign dout[i] = dout_pre[i];
          `endif//}
      end
   end
   else begin:no_force_x_to_zero
     assign dout = dout_pre;
   end
  endgenerate
 
endmodule
*/



/* reg
module sirv_sim_ram
#(parameter DP = 512,
  parameter FORCE_X2ZERO = 0,
  parameter DW = 32,
  parameter MW = 4,
  parameter AW = 32 
)
(
  input             clk, 
  input  [DW-1  :0] din, 
  input  [AW-1  :0] addr,
  input             cs,
  input             we,
  input  [MW-1:0]   wem,
  output [DW-1:0]   dout
);

    reg [DW-1:0] mem_r [0:DP-1];
    reg [AW-1:0] addr_r;
    wire [MW-1:0] wen;
    wire ren;

    assign ren = cs & (~we);
    assign wen = ({MW{cs & we}} & wem);



    genvar i;

    always @(posedge clk)
    begin
        if (ren) begin
            addr_r <= addr;
        end
    end

    generate
      for (i = 0; i < MW; i = i+1) begin :mem
        if((8*i+8) > DW ) begin: last
          always @(posedge clk) begin
            if (wen[i]) begin
               mem_r[addr][DW-1:8*i] <= din[DW-1:8*i];
            end
          end
        end
        else begin: non_last
          always @(posedge clk) begin
            if (wen[i]) begin
               mem_r[addr][8*i+7:8*i] <= din[8*i+7:8*i];
            end
          end
        end
      end
    endgenerate

  wire [DW-1:0] dout_pre;
  assign dout_pre = mem_r[addr_r];

  generate
   if(FORCE_X2ZERO == 1) begin: force_x_to_zero
      for (i = 0; i < DW; i = i+1) begin:force_x_gen 
          `ifndef SYNTHESIS//{
         assign dout[i] = (dout_pre[i] === 1'bx) ? 1'b0 : dout_pre[i];
          `else//}{
         assign dout[i] = dout_pre[i];
          `endif//}
      end
   end
   else begin:no_force_x_to_zero
     assign dout = dout_pre;
   end
  endgenerate

 
endmodule
*/
